Alif Semiconductor /AE101F4071542LH_CM55_HE_View /LPCPI /CAM_CFG

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CAM_CFG

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (Val_0)WAIT_VSYNC 0 (Val_0)VSYNC_EN 0 (Val_0)ROW_ROUNDUP 0 (Val_0)PCLK_POL 0 (Val_0)HSYNC_POL 0 (Val_0)VSYNC_POL 0 (Val_0)DATA_MODE 0 (Val_0)MSB 0 (Val_0)CODE10ON8

DATA_MODE=Val_0, WAIT_VSYNC=Val_0, VSYNC_POL=Val_0, HSYNC_POL=Val_0, ROW_ROUNDUP=Val_0, PCLK_POL=Val_0, CODE10ON8=Val_0, VSYNC_EN=Val_0, MSB=Val_0

Description

Camera Configuration Register

Fields

WAIT_VSYNC

Capture video frame on the rising edge of VSYNC.

0 (Val_0): Start video capture without waiting for VSYNC

1 (Val_1): Start video capture on rising edge of VSYNC

VSYNC_EN

Capture data when VSYNC is high.

0 (Val_0): Capture data regardless of VSYNC status

1 (Val_1): Capture data when VSYNC is high

ROW_ROUNDUP

Round up pixel data to 64-bit at the end of each row.

0 (Val_0): Not round up

1 (Val_1): Round up pixel data to 64-bit at the end of each row

PCLK_POL

Set camera PIXEL_CLK polarity.

0 (Val_0): Not invert external camera PIXEL_CLK

1 (Val_1): Invert external camera PIXEL_CLK

HSYNC_POL

Set camera HSYNC polarity.

0 (Val_0): Not invert HSYNC input

1 (Val_1): Invert HSYNC input

VSYNC_POL

Set camera VSYNC polarity.

0 (Val_0): Not invert VSYNC input

1 (Val_1): Invert VSYNC input

DATA_MODE

Select video data mode.

0 (Val_0): 1-bit

1 (Val_1): 2-bit

2 (Val_2): 4-bit

3 (Val_3): 8-bit

MSB

Select MSB/LSB Valid only when [DATA_MODE] field is set to 1-/2-/4-/8-bit.

0 (Val_0): LSB

1 (Val_1): MSB

CODE10ON8

Special coding: transfer 10-bit coding over 8-bit data bus. Valid only when [DATA_MODE] field is set to 8-bit.

0 (Val_0): Disable special 10-bit coding

1 (Val_1): Enable special 10-bit coding

Links

() ()